Approach to the manufacturing of monolithic 3-dimensional high-rise integrated-circuits with vertically-stacked double-sided fully-depleted silicon-on-insulator transistors

ABSTRACT

Method to fabricate high-rise three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all the other known methods and prior arts to fabricate or manufacture 3D-ICs in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAs in monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.

BACKGROUND OF THE INVENTION

As the Semiconductor industry is entering the era that foresees the end of miniaturization of the Silicon transistor, engineers are already considering newer approaches to boost the device density, the efficiency and the performance of the logic and the memory Chips without necessitating the move to smaller transistors. Although Three-Dimensional (3D) circuits are nothing new given that Integrated-Circuits (ICs) are routinely packaged nowadays one on top another via wire-bonds or large copper pillars called Through-Silicon-VIAs (TSVs) that vertically connect the ICs together, the concept has still limitations. For one thing, these 3D-Packages are interconnecting the subsystems together and not their discrete components. This is consequently limiting the density of 3D interconnections, and the overall Chip performance. Further, even in substituting wire-bonds with TSVs the resulting effects from RC-delays and higher impedances between subsystems were reported to still be below desired expectations. They were specifically reported to still cause reduced electrical performance, high parasitic power consumption, and poor heat dissipation. Among the many published literatures detailing on these effects are those by Pulkit Jain et al., “Three Dimensional Integrated Circuit Design”, Chapter 3: Thermal and power delivery Challenges in 3D ICs, pp. 33-61, Springer Science+Business Media, LLC, 2010; and, Mohammad A. Ahmed et al., “Delay and power optimization with TSV-aware 3D floorplanning”, 2014 15^(th) International Symposium on Quality Electronic Design (ISQED), pp. 189-196, Santa Clara, Calif., March 2014.

The today's cutting-edge advancements in the integration of 3D-ICs have only recently started allowing full monolithic vertical stacking of the active transistors on top of one another. A method to this vertical monolithic integration uses exact same technique that is utilized nowadays in the standard commercial productions of Silicon-On-insulator (SOL) wafers, that is: The Smart-Cut approach, also known as Ion-Cut. It was initially described and demonstrated by M. Bruel, B. et al., “Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding”, Japanese Journal of Applied Physics, 36, 1636, 1997, and was continuously improved upon over the past 20 years. Several Patents are already filed on the manufacturing of monolithic 3D-ICs using this Smart-Cut approach, among which are the works by, Zvi Or-Bach et al., U.S. Pat. No. 9,564,432 B2, “3D Semiconductor Device and Structure”, Feb. 7, 2017; and, Zvi Or-Bach, U.S. Pat. No. 9,577,642 B2, “Method to Form a 3D Semiconductor Device”, Feb. 2, 2017. The core concept in these newly filed patents is founded on vertically stacking through Smart-Cuts thin layers of virtually defect-free Silicon with their Inline dielectrics firmly bonded together and sandwiched between these layers. The active transistors are designed and built on these vertically stacked thin layers of Silicon that are separated from each other with Inline dielectrics and Inline interconnect-Layers (these include planar interconnects and VIAs). Vertical TSVs cut through these stacked layers of Silicon and vertically wire transistors together. The transistors become then monolithically placed on top of one another. Early gross results from this method to monolithic 3D integration already reported on much shorter overall wires between the transistors. This appears to already tackle the major and well-known wire-delay problems in today's commercial ICs and that are caused from no other than the inter-wirings of the planar transistors through piles of vertically stacked Metal layers that are separated from each other with no other than thick Inline dielectrics and connecting VIAs. It was specifically reported that more than an order of magnitude improvement in the “Power×Area×Delay” figure-of-merit does result. Also reported were ˜34% consequent shorter wire-lengths, ˜26% improvement in power consumption, and more than 50% reduction of die-area. Relating findings were reported by Zhou et al., “Implementing a 2-Gbs 1024-bit ½-rate low-density-parity-check code decoder in three-dimensional integrated circuits”, Proceedings of the 25^(th) IEEE International Conference on Computer Design (ICCD), pp. 194-201, October 2007; and, Neela Lohith Penmetsa et al., “Low Power Monolithic 3D IC Design of Asynchronous AES Core”, Proceedings of the 2015 21^(st) IEEE International Symposium on Asynchronous Circuits and Systems, May 2015. This same vertical monolithic stacking also demonstrated strong potential to the continuation of Moore's law by continuously increasing the number of transistors per unit-area through this vertical expansion. Gains in device densities that are equivalent to two generations of Dennard scaling were reported by Synopsys, Proceedings of the 3D Architectures for Heterogeneous Integration and Packaging, December 2010.

Despite the above performance enhancements through monolithic 3D device integration (monolithic 3D-ICs), more power-efficient high-speed circuits still require more reduced RC-delays and shorter interconnects. Capacitive coupling through the dielectric sidewalls between the TSVs and the Silicon substrates was reported to impose limitation on higher speed. This was described in many literatures among which is the work by, Dae Hyun Kim et al., “Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling”, IEEE Trans. Comp. Pack Manuf. Tech., vol. 1, no. 2, February 2011. Additionally, the use of these large bulky TSVs to vertically connect devices together can have many related manufacturing snags and it generally delivers limited capabilities to vertical integrations.

BRIEF SUMMARY OF THE INVENTION

Beyond the 90 nm CMOS technology-node the Backend RC-delays from the Inline interconnects alone became sufficiently pronounced and started to largely dominate the speed of CPUs. In today's most advanced systems these RC-delays are already two to four orders of magnitude higher than the device Gate delays. This is ironically negating in the first place all and any performance enhancements from the Frontend. Furthermore it is well known that more than 50% of the total dynamic power dissipated in processors is consumed in Inline interconnects. Because of these, any and all further progress to the performance and to the power-efficiency of microprocessors, microcontrollers and other ICs have become largely dependent nowadays on no other than reducing RC-delays and parasitic power consumed in Inline interconnects. In addressing some of these issues, the prior art to monolithic 3D-ICs is vertically stacking layers of Silicon to monolithically place transistors on top of one another in precise and specific alignments that ensure on average much shorter Inline interconnects than if these transistors were all placed instead in same Silicon layer (or Silicon plane) and interconnected. Despite its initial impressive enhancements to performance (as were reported by, Zhou et al., 25^(th) IEEE ICCD, pp. 194-201, October 2007), one pitfall from this prior art is that TSVs are required to interconnect transistors in the different vertically stacked Silicon layers when two and more layers are stacked. This requires the TSVs to cut through the Silicon of the devices (transistors) that are to be connected and travel at least the vertical distance of one interconnect-Layer (one Metal-Layer) from the Silicon surface of these devices, and from this interconnect-layer additional lateral interconnects connect to the designated terminals of the transistors. This is being illustrated in the FIG. 1 Cartoon schematic for the prior-art. To vertically interconnect through the 3D architecture of this prior-art from the top interconnect-Layer of the bottom transistor to the Gate terminal of the higher vertical transistor a total equivalent-length from TSV and interconnects equaling: 2×Y+Lx+tsi is required for just this one terminal-to-terminal connection. To also interconnect the other two terminals of same bottom and higher transistors together would require the addition of up to two more TSVs and up to two more wirings having a similar total equivalent-length. The invention of this patent reduces this equivalent-length by factor of more than two. This consequently reduces the impedances, the RC-delays and the power consumed due to this same equivalent-length by same factor. As the other Cartoon schematic of FIG. 1 that describes the new-approach (of this patent) shows, a significant portion from this total equivalent-length equaling anywhere between: tsi+Y and tsi+Y+Lx is trimmed in each vertical terminal-to-terminal connection. This is expected to significantly reduce the RC-delays and the speed in logic and Memories. This new-approach as is shown in FIG. 1 constitutes one 3D-IC module made of two Silicon layers (L1 and L2) with each having one high interconnect-layer above it (HM1) and one low interconnect-layer below it (LM1). The HM1 of L1 that connects to the Source of the bottom transistor in L1 (T1) is directly wired to the LM1 of L2 that connects to the Gate of the higher transistor in L2 (T3). Similarly, the HM1 of L1 that connects to the Drain of T1 and Source of T2 in L1 is directly wired the LM1 of L2 that connects to the Source of the higher transistor in L2 (T4). These shorter top-to-bottom wirings and their consequent effect on reducing RC-delays and power consumption are made possible through the use of Dual-Sided Fully-Depleted-Silicon-On-Insulator (DS-FD-SOI) MOS transistors as main building-block to this monolithic 3D integration. DS-FD-SOI MOS are devices that are fully immersed in Inline dielectric and can equally connect their Gates, Drain and Source terminals to those of other similar transistors and electric components from their top-side as well as from their opposite bottom-side (as is shown in FIG. 1). This is being realized through having their Drain, Source and Gate Contacts symmetrically dual-sided and equally distributed on the top and the opposite bottom side (or surface) of their ultra-thinned active Silicon (as is shown in FIG. 2). This allows to directly wire the top Contacts of one transistor to the bottom Contacts of another that is positioned above it. They further operate in Full-Depletion mode due to the ultra-thinness of their virtually defect-free active Silicon and this further brings the added advantage of higher device performance, good subthreshold characteristics, and a denser level to 3D integration simply due to the ability to vertically stack much larger number of these defect-free ultra-thinned Silicon layers. Through this embodiment, the Secondary Gates of the DS-FD-SOI MOS transistors that remain untied to circuit can function to dynamically and digitally control both power and performance.

Main reason for specifically implementing this Dual-sided approach to Contacts with the Fully-Depleted-Silicon-On-Insulator device technology is largely due to this device distinctive ability that allows it to dynamically tune and vary its Threshold-Voltage (VT) to accommodate best tradeoffs between power and performance. Because of its strong electrostatic coupling between its two Gates it can as needed dynamically and substantially increase its VT for lowest off-state power and decrease it for highest performance. A 1.6× increase in CMOS switching speed (Fmax) was reported from these devices due to no other than tuning the bias on the secondary Gates to its highest rail, and a device Off-state leakage as low as 1 PA/μm was similarly reported from tuning same bias to its opposite lowest rail; this further appears to be just the start as further enhancements to auto-tune the performance and the power over wider dynamic range are being continuously made (Source: Globalfoundries publication PO22FD-10, Introducing the 22FDX™ 22 nm FD-SOI Platform from GLOBALFOUNDRIES; March 2016). No other existing device technology today can deliver such wide dynamic shifts in VT, in off-state power and in performance from no other than controlling one fully independent secondary knob while all the primary Gates remain tied to their circuit modules. This permits maximizing battery-life by dynamically auto-adjusting active and leakage powers to accommodate rapidly changing conditions (e.g. sudden surge of strong winds in face of flying drones, sudden need for faster computing-power for purpose of detection and tracking, etc . . . ). It further offers greatest potential to new emerging cutting-edge technologies such as the Internet-Of-Things (IOT) and Unmanned-Areal-Vehicles (UAV or drones) that necessitate that the ultra-fast but power hungry modules remain in sleep-mode till they arc awakened by particular sensors so they can rapidly perform their required ultra-fast computations and data analysis before going again back to sleep-mode.

Through this new patented approach to monolithic 3D-ICs drastic enhancements to both computing speed and energy-savings result from its shorter passive interconnects (reduced RC-delays and less power consumed in interconnects), consequently the speed advantage from the down-scaling of the Gate-lengths that has become virtually repressed nowadays because of none other than these same RC-delays is partially regained and with even better power-efficiency. Separately, through fully eliminating (or substantially reducing) TSVs, a much denser level of device integration is consequently gained; this is true for the Logic and for the Memory modules (these can be any forms of Memories: SRAMs, DRAMs, MRAMs, etc . . . ).

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1: Cartoon drawings showing a side-by-side comparison of the prior-art that requires the use of TSV's to interconnect transistors positioned on top of one another, and the new-approach (of this patent) that utilizes Dual-Sided transistors to eliminate this use of the TSV's and shorten the Inline interconnections.

FIG. 2: Cartoon drawings depicting the transistor structures of DS-FD-SOI MOS transistors.

FIG. 3: Cartoon drawings illustrating some main advantages from using the DS-FD-SOI MOS transistor as building-block to monolithic 3D-ICs.

FIG. 4: Simplified Cartoon drawings illustrating the process flow to the fabrication of the Base-Layer.

FIG. 5: Cartoon drawings illustrating the two separate approaches to bonding and vertically stacking the Silicon layers.

FIG. 6: Cartoon drawings illustrating and summarizing the two separate approaches and their relating processes to the build-up of integrated monolithic 3D-ICs. (All drawings are shown for case of thermo-compression Interconnect-to-Interconnect bonding).

DETAILED DESCRIPTION OF THE INVENTION

The approach can vertically integrate any number of Silicon layers with any number of high and low Inline interconnect-layers in each Silicon layer. The number of low Inline interconnect-layers in any Silicon layer can be different than the number of its high Inline interconnect-layers. Aside from the shorter top-to-bottom interconnects that this new-approach (of this patent) brings by enabling to directly connect the top Contact(s) of one device to the bottom Contact(s) of another, it has few additional advantages over all prior arts: 1) It allows more ease and flexibility to interconnect the transistors in same Silicon layer (or Silicon plane) by interconnecting these transistors from above and/or from below. This can further reduce the lengths, the RC-delays and the power consumed in interconnecting the devices (transistors) that are laid in same Silicon layer. 2) It enables active 3D-routing of electric signals with purposely switched On/Off devices. This enables reconfiguring the Hardware architecture in 3D making therefore this approach to monolithic 3D-ICs most suited to reconfigurable computing and the next generation 3D-Field-Programmable-Gate-Arrays. The Cartoon schematics of FIG. 3 illustrate these three features of this new approach (of this patent) to monolithic 3D-ICs.

With Silicon thinness as small as 3-20 nm, and Gate lengths smaller than 10 nm, these Double-Sided transistors that operate in full-depletion-mode will have nanometric volumes comparable or potentially even smaller than nanowires and Carbon-NanoTubes (CNTs) transistors. Simulated scaling trends on conventional Fully-Depleted-SOI MOS as were reported by, Rongtian Zhang et al., “Low-Power High-Performance Double-Gate Fully-Depleted SOI Circuit Designs”, IEEE Trans. Elec. Dev., vol. 49, No. 5, pp. 852-862, May 2002, suggest current density as high as 2.8 mA/μm at only 0.6V Drain bias in device having 22 nm Gate-length. This was largely due to the ultra-thin BOX and Silicon in this device, and to its forward-biasing through its two Gates. It is believed that when the Silicon film gets excessively thinned and both Gates get forward-biased the entire barrier throughout the thinned Silicon can become pronouncedly lowered and the entire Silicon between the Gates can conduct. This gives substantially lower channel resistance and very high currents. A key is to ultra-thin the Silicon film enough to confine and distribute carriers throughout the thickness of this thinned Silicon film and yet to maintain it relatively thick enough to maintain higher channel conductance. These numbers well surpass the 1 mA/μm current density that are reported from today's CNT transistors having Gate-lengths as small as lOnm and that are somewhat close to the current densities being reported from the conventional Fully-Depleted-Silicon-On-Insulator transistors having thicker BOX and thicker Silicon films. It similarly surpasses what is being reported today's from Silicon nanowire transistors. Today's typical current densities from CNT and Silicon nanowire transistors are being reported in many literatures among which are the most recent work of Qiu et al., “Scaling carbon nanotube complementary transistors to 5 nm gate lengths”, Science 355, pp. 271-276, January 2017.

First phase of the fabrication of this 3D-IC architecture starts by manufacturing the so-called Base-Layer; this is the very bottom Semiconductor layer atop which all the additional ultra-thin Silicon films (or Semiconductor layers) will be stacked with their Inline interconnects and dielectrics. Unlike in the design and manufacturing of Silicon-On-Insulators devices and Integrated-Circuits where all work begins on pre-manufactured Silicon-On-Insulator Wafers, these 3D-IC architectures necessitate construction of both; their ultra-thin Silicon films on which the planar footprints of devices are laid, and their insulating Inline dielectric and interconnect-Layers (these interconnect-Layers are made of both planar interconnects and VIAs).

The conventional Smart-Cut approach to ultra-thinning the stacked Silicon is not recommended in this 3D fabrications process. This is due to the multiple Heat Cycles that this new process to 3D-fabrication requires prior to bonding the Wafers together through their Inline dielectrics; if Hydrogen implant (for Smart-Cut) gets processed prior to these required Heat Cycles, blisters and possible cracks in the seed-Wafer can start to generate even prior to its bonding. These required Heat Cycles are being described in the Step-3 of this fabrication process. Because of this, the Bonded-and-Etchback-SOI (BEBSOI) process approach is the more preferred method to transferring and vertically stacking the ultra-thin Silicon layers through this 3D fabrication process. Recent technological advancements in the manufacturing of Semiconductors can allow today nano-precision polishing of the surface of Semiconductor Wafers through several new innovative and different process techniques such as: MagnetoRheological Finsish (MRF) and Plasma Chemical Vaporization Machining (PCVM). It is reported on the capability from these techniques to successfully scale from removing microns of materials to removing nanometers of material, while still improving thickness, flatness and within-wafer thickness uniformity. Published data reported on successfully ultra-thinning Silicon through these techniques down to 13 nm with an about thickness variation of 2 nm only. Among the many works that detail on such and similar results are; Mori Yet al., “Development of Plasma Chemical Vaporization Machining”, Rev. Sci. Instrum. 2000, 71:4627-4632; Mori Yet al., “thinning of silicon-on-insulator wafers by numerically controlled plasma chemical vaporization machining”. Rev. Sci. Instrum. 2004, 75: 942-946; and, Marc Ticard et al., “Prime Silicon and Silicon-On-Insulator (SOI) Wafer Polishing with Magnetorheological Finishing (MRF)”, Proceedings of IMECE '03, Washington, D.C, Nov. 15-21, 2003. It is this capability through such more recent PCVM and MRF processes and with potentially few additional processing steps to ultra-thin the Silicon films down to nanoscale precisions that makes the BEBSOI process feasible today to transfer and vertically stack ultra-thin layers of Silicon films with nanoscale dimensions.

Several different approaches can be undertaken to the fabrication of the Base-Layer:

One approach is to implant an Etch-Stop-Layer (ESL) through the front surface of the seed-Wafer. The ESL can be made of a high dose of Boron implanted at medium energy (<200 KeV), followed with the growth of low-doped epitaxy onto it. This epitaxial layer will then become the SOI Ultra-thinned Silicon layer in which devices are fabricated after bonding the seed-Wafer through its dielectric atop this grown epitaxy to the dielectric surface of a Handle-Wafer and etching its Back Silicon and ESL prior to ultra-thinning it to its precision nanoscale thickness through MRF and/or PCVM. Other forms of ESLs (e. g. SiGe) may also be utilized instead.

Another similar approach is to Implant Carbon through the front Silicon of the seed-Wafer. Carbon is electrically-inactive in Silicon and when implanted at temperatures close to 500 degC Crystal damage is lowered or minimized. At optimal implant energies and doses, this implanted Carbon forms a very effective ESL 100 nm below the front surface of the seed-Wafer that slows or stops the etch of Back Silicon in this seed-Wafer after its bonding through its dielectric atop its front Silicon to the dielectric surface of a Handle-Wafer and prior to the MRF and/or PCVM to achieve the target nanoscale Silicon thinness. Other species (e. g. Nitrogen) may also be implanted instead into the seed-Wafer to form ESLs. Carbon can be also implanted instead through the Back Silicon after bonding the seed-Wafer to the Handle-Wafer and after some initial grinding and etch are done to thin this Back Silicon down to few hundreds nanometers.

Other approach can omit the use of ESL all together and rely instead on precision numerically controlled etch of the Back Silicon of the seed-Wafer after its bonding through its dielectric atop its front surface to the dielectric surface of a Handle-wafer and prior to the final PCVM and MRF finish. Hydrogen implant can also be performed through this back Silicon so to Smart-Cut close to 100 nm from it while maintaining good relative nanoscale within-Wafer uniformity on this Back Silicon prior to MRF and/or PCVM.

Step-1: Front surface of the seed-Wafer is thoroughly cleaned with the standard Cleans that are used today in the most advanced CMOS processes. ESL and/or epitaxy can then be formed. Nitride antireflective coating is deposited, and Isolation-trenches are then patterned, etched, and filled with dielectric. The Nitride film is then selectively removed. This is followed with a very thorough Clean of the surface. The resulting step-height (sh) of the Isolation-trenches is used for precise on-wafer alignment.

Step-2: N- and P-regions are then patterned, implanted and the devices are fabricated in following the today's standard CMOS processes. These include: The processing of highest quality Gate dielectric (lower temperatures (≤900 DegC) are recommended for reasons that are explained later), Silicide formation, anneals, patterning, etch and the formations of trenched-Contacts, Inline interconnect-Layers and Inline dielectric. These also include all the layering films that are typical to today's CMOS processes (e. g. Gate Spacer, Ti/TiN films for Contact adhesions, Tantalum to prevent diffusion of Copper from interconnect-Layers when Copper is used as Inline Metal for interconnects, Nitride and silicon-Carbide as ESLs, etc . . . ). Peak temperature for the Rapid-Thermal-Anneal (RTA) can be reduced to 700-1000 DegC for reasons that are also explained later. Generally fewer interconnect-Layers are processed on each side of the Silicon layers (typically about one to four interconnect-Layer(s)), but depending on the complexity of the particular Integrated-Circuit these can be more. Carbon-doped low-K Inline dielectric is typically recommended for lowest RC-Tau, but other Inline dielectrics can always be used instead.

Step-3: Because the deposited Inline dielectric can or is known to outgas and creates voids in the bond interface upon being subjected to high temperatures after the bonding of any two wafers through their dielectrics, the seed-Wafers undergo prior to this bonding a high temperature anneal that outgases any by-products or gas molecules that were absorbed during the deposition of their Inline dielectrics. This pre-bond anneal is typically between 800 DegC and 1200 DegC. When using pre-bond anneals above or close to 1000 DegC, tough Metals (e. g. Tungsten) are deposited prior as interconnect-Layers. Similarly, when same high temperatures pre-bond anneals are used, Silicides that are much more stable than Nickel-Silicide at and around such high temperatures are formed prior during the Frontend processing. Such Silicides include: WSi₂, MoSi₂, TaSio₂, and CoSio₂. CMP follows this pre-bond anneal and the two Wafers are next bonded together through their dielectrics. A post-bond anneal is then performed to strengthen this bond and the two Wafers become one Wafer.

Step-4: Grinding of the Back Silicon is then performed so to thin it down to about 30-50 μm. Grinding is recommended first because of its high thinning rate but standard CMP can also be used instead. This is a two-step process that includes a coarse grinding (at ˜5 μm/s) and a subsequent fine grinding (at ˜1 μm/s). The second step is necessary to remove most of the damage layer created by the coarse grinding step and reduce surface roughness. Additional thinning processes are performed next to further thin down this Back Silicon. These may include combinations of dry/wet etching and CMP in aim to substantially further reduce the thickness of this Back Silicon down 100 nm-250 nm prior to MRF and or PCVM. A final MRF finish remove few hundreds Angstroms from the Back Silicon, exposing the Isolation-trenches (the depth of the Isolation-trenches is specifically gauged in the Step-1 so to expose these trenches at the other side of Silicon through this final polishing step). SOI Silicon film thickness as little as 3 nm-40 nm can be achieved through this process.

Step-5: A very high selective etch of the dielectric of the Isolation-trenches is then done so to recess them for precision Back-to-Front Silicon alignment. The “rectangular” quality of the etched Isolation-trenches is critical for that purpose. This can be done by depositing Sacrificial-Light-Absorbing-Material (SLAM) after this recess followed with Photoresist, patterning and exposure to etch the SLAM inside these Isolation-trenches. Isolation-trenches are then re-filled with dielectric, rest of SLAM is removed and the resulting step-height (sh) in these trenches is used for same on-wafer alignment as to what was used on the other side of Silicon. This can very closely align the two Gates on the two different sides of the Silicon film.

Step-6: This other side of the Silicon is then processed for its Frontend and backend. Second Gate can either have exact same insulator thickness as the other Gate or a slightly different thickness. Since Copper Inline Metals melt at temperatures equal or higher than 1080 DegC and all Silicides become unstable above 900-1000 DegC, lower temperatures (≤700-900 DegC) are recommended in the formations of all Gate dielectrics. Similarly lower RTA anneals are also recommended. The use of tougher Metals for Inline interconnect-Layers (e.g. Tungsten) is also a possibility.

All the above process steps for the fabrication of the Base-Layer are clearly illustrated in the Cartoon schematics of FIG. 4.

The Smart-Vertical-Stacking of layers of ultra-thinned Silicon films is then followed. Two separate approaches can be utilized to bond the different Silicon layers with their Inline dielectrics and interconnects on top of one another:

One approach directly thermally-bonds the different Silicon layers together through both their Inline dielectrics and interconnect-Layers. For this, the Inline dielectrics of the Silicon layers to be bonded are first thoroughly polished to expose the Inline interconnect-Layers. The pitch of the planar interconnect-Layer to be bonded is higher than that of interconnect-Layers that are closer to Silicon. This pitch is purposely designed larger than the typical accuracy of today's Inter-substrate alignment on 300 mm Wafers so to make this direct interconnect-to-interconnect bonding feasible. The accuracy today of commercially available wafer-to-wafer alignment tools is 0.18 μm and with continued efforts in developing Wafer-to-Wafer alignment tools, more precise accuracy toward the deep-sub-micrometer regime of the Wafer-level process can be achieved with tighter processing control. This direct interconnect-to-interconnect bonding can either use low temperature Wafer-level thermo-compression bonding or higher temperature bonding. Copper Metals are very attractive choice for the low temperature thermo-compression bonding in terms of lower cost and the ability to bond Copper at temperatures as low as 250-300 DegC.

The other approach wires the different Silicon Layers on top of one another by bonding the Silicon layers together through their Inline dielectrics. This is then followed with a deep etch through the Isolation-trenches down to the higher interconnect-Layer of the bottom Silicon layer. SLAM is then deposited to fill this deep etched trench. This is followed with patterning and etching for interconnecting the higher interconnect-Layer of the bottom Silicon layer to the lower interconnect-Layer of the top Silicon Layer. Finally inter-wires are formed (e.g. with Sputtering & Electroplating) to physically interconnects the two Silicon layers together. While forming these inter-wires selective etch of the SLAM is done first to expose the ESL in the higher interconnect-Layer of the bottom Silicon layer. This is followed with another selective etch of the Inline dielectric to expose the ESL in the lower interconnect-Layer of the upper Silicon layer. The etch chemistry is then switched one last time to etch the ESLs in both interconnect-Layers.

FIG. 5 shows simple representative Cartoon schematics highlighting the process steps in both techniques.

Two separate paths to vertical stack the Silicon layers can be followed:

One technique stacks one entire Base-Layer after the other (Layer-by-Layer transfer). In this, the process steps 1 through 6 of FIG. 4 are first completed on other wafers to be stacked. These new Base-layers of processed Silicon are then, one after the other, bonded and their Back Silicon is removed prior to the bonding of next Base-Layer. This technique has the disadvantage of requiring deeper etch through the Isolation-trenches to inter-wire the higher interconnect-Layer of the bottom Silicon layer to the lower interconnect-Layer of the top Silicon layer.

The other technique uses only the Step-1 and Step-2 of FIG. 4 on other wafers to process their front Silicon and vertically stack and bond them one at a time. After the bonding of each seed-Wafer its back Silicon is then ultra-thinned and processed (Half-Layer Transfer & Process”).

FIG. 6 shows summary of the two separate approaches and their relating processes to the build-up of integrated monolithic 3D-ICs. (All drawings are shown for case of thermo-compression Interconnect-to-Interconnect bonding).

Limited number of electrically-inactive TSVs can be always utilized as conductive heat spreaders to dissipate the intense heat through thermally-efficient 3D-IC package 

What is claimed is:
 1. The use of Dual-Sided Contacts to Drain and Source to shorten Inline interconnects between any two devices (e.g. transistors) that are vertically stacked on top of one another in Three-Dimensional Integrated-Circuits (3D-ICs); Dual-Sided Contacts are Ohmic Contacts that are applied or distributed on two opposing sides (surfaces) of a semiconductor; this shortening of the Inline interconnects is accomplished through enabling the top Contacts of the bottom devices to interconnect to the bottom Contacts of higher vertically stacked devices; this claim is specific to the mid-section process; it therefore extends to all and any devices and transistors to which Dual-Sided Contacts are or can be processed;
 2. The use of Dual-Sided-Fully-Depleted-Silicon-On-Insulator MOS (DS-FD-SOI-MOS) transistors as building-blocks to monolithic Three-Dimensional Integrated-Circuits (3D-ICs) for high on-state performance and low off-state leakage; the high performance and low off-state leakage are largely attributed from the capability to modulate this device Threshold-Voltage (VT) through independently controlling and tuning one of its two Gates to accommodate best off-state power and performance; higher performance is also largely attributed to the much shorter Inline interconnects between the 3D-integrated device, included are the Inline interconnects between devices (transistors) that are vertically stacked on top of one another; these DS-FD-SOI-MOS transistors can be used to form all Logic and Memory modules in 3D-ICs (these are any forms of Memories: SRAMs, DRAMs, MRAMs, etc . . . ); DS-FD-SOI MOS are transistors that are fully immersed in Inline dielectric and have exact same Contacts to their Drain and Source, and same or similar insulating Gates to their front-surface and back-surface, (back-surface is their reverse-side surface relative to their front-surface); they are solely made of electrically active Silicon without the thick bulky substrates that induce unwanted parasitic effects, contribute to unnecessary increase in the heights of 3D-ICs, and cause lower electric conductivities from interconnecting the vertically stacked devices through them with Through-Silicon-VIAs (TSVs); the devices channels can be any forms, strained or unstrained, recessed (having raised Source and Drain) or un-recessed, and the semiconductor films can be either composed of plain Silicon or with its compounds (e.g. SiGe);
 3. The use of DS-FD-SOI MOS transistors as special-purpose switches for active 3D-routing that can reconfigure Hardware architectures in 3D;
 4. The technique to bond two vertically stacked Silicon layers together through their Inline dielectrics and then pattern and form the inter-wires that connect these two layers together; this is being accomplished with a deep trench etch through the Isolation-trenches down to the higher interconnect-Layer of the bottom Silicon layer; SLAM is then deposited to fill this deep etched trench; this is followed with patterning and etching for interconnecting the higher interconnect-Layer of the bottom Silicon layer to the lower interconnect-Layer of the top Silicon layer; finally inter-wires are formed (e.g. with Sputtering & Electroplating) to physically interconnect (or inter-wire) the two Silicon layers together; while forming these inter-wires selective etch of the SLAM is done first to expose the ESL in the higher interconnect-Layer of the bottom Silicon layer; this is followed with another selective etch of the Inline dielectric to expose the ESL in the lower interconnect-Layer of the upper Silicon layer; the etch chemistry is then switched one last time to etch the ESLs in both interconnect-Layers;
 5. The technique to directly thermally-bond the different Silicon layers together through both their Inline dielectrics and their interconnect-Layers; for this, the Inline dielectrics of the Silicon layers to be bonded are first thoroughly polished to expose their Inline interconnect-Layers; this is then followed with thermo-compression bonding. Interconnect-layers made of Copper Metals are good choice for this bonding technique as they can bond at high temperatures (˜1000 DegC), and at temperatures as low 250-300 DegC.
 6. The technique to align for lithography the front surface of a thinned layer of Silicon to its back surface through forming deep Isolation-trenches on one surface of the seed-Wafer, fully processing that one side, and bonding it through its Inline dielectric to the dielectric surface of a Handle-Wafer. The Back Silicon of this seed-wafer is then excessively thinned through etch and/or polish to expose these Isolation-trenches from their opposite side (surface). These exposed isolation-trenches can then be selectively etched and recessed, and can be used for precision front-to-back alignment. 